FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics

Abstract

Squaring and cubing units have importance in various applications in digital signal processing. This paper proposes new squaring architectures based on vedic mathematics sutra of Antyayordashakepi and Dwandwa Yoga (Duplex). Further a new cube architecture based on proposed square and Anurupya sutra is also proposed. The squaring units were implemented for bit size of 8 and 16 while cube was implemented for bit size of 8 on kintex 7 FPGA board. Proposed squarers provided with power delay product of 106.99 and 45.65 whereas cube had power delay product of 444.47 for 8 bits of input.