PhD forum: BiSeeMos: A fast embedded stereo smart camera

Abstract

This paper presents a new embedded stereo vision system called BiSeeMos. This system has been designed for fast stereo vision computation up to 160 frames per second at a resolution of 1024 by 1024 pixels. The system's heart is a Cyclone III FPGA from ALTERA Corporation with 119,088 reconfigurable logic elements, 3,888 Kbits of memory and 288 embedded multipliers. A versatile vision framework has been implemented in the system along with a Census stereo vision algorithm to validate the platform.