Power and Performance Tabu Search Based Multicore Network-on-Chip Design

Abstract

This paper presents a Tabu search based approach for the topology synthesis of application-specific multicore architectures using an automated design technique. The Tabu search method incorporates multiple objectives in order to generate an optimal NoC topology which accounts for both power and performance factors. The method generates a system-level floorplan in each major stage of the topology synthesis. By incorporating the floorplan information, it is possible to attain accurate values for power consumption of the routers and physical links, as well as manage the interconnections within the system. The technique also includes a contention analyzer that assesses performance and omits any potential bottlenecks. The contention analyzer uses a Layered Queuing Network approach to model the rendezvous interactions amongst system components. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of the proposed technique.