High Speed Sixty Four Bit Vedic Multiplier

Abstract

Multiplication operation is the core of many techniques like convolution, correlation, fast fourier transform etc. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. Optimising multiplier (in terms of delay or area or power) will have a huge impact on system performance. One of the methods adopted to reduce delay is the use of Vedic Multiplier based on “Vedic Mathematics Sutras”. In this project “Urdhava - Tiryakbhayam” Sutra is used to perform multiplication and is simulated and implemented in Xilinx ISE Design 14.7