FPGA Acceleration Architecture Design and Implementation of Satellite Ground Fusion High-Speed Transmission Link

Abstract

Using FPGA to realize symbol level data processing of high-speed satellite ground fusion transmission link, and taking it as the core device of data processing, can effectively improve the processing performance of the system. It can be applied to the transmission and processing of large capacity real-time signals in the scene of satellite ground fusion. Aiming at the problems of large delay, large frequency offset, and multipath effect in the high-speed link of satellite ground fusion, this paper proposes a hardware acceleration architecture based on a standard processing platform and FPGA. The symbol level high-capacity data processing is implemented in FPGA and the upper data receiving function is implemented on DSP. After receiving the data, through time synchronization, frequency synchronization, channel estimation, FFT, resource de-mapping, demodulation, serial to parallel conversion, descrambling, these modules complete the signal level data processing of satellite ground fusion high-speed transmission link.