Noise analysis and optimization of power constrained integrated inductive degradation LNAs

Abstract

When the matching inductors of low noise amplifiers (LNAs) are moved from off chip to on chip, their noise contribution cannot be neglected. This paper investigates the noise performance of an integrated source inductive degradation LNA, analyzes the noise contribution of its input matching inductors, and proposes a noise optimization method for the input matching network design of a power constrained LNA. The result was verified with a 2GHz LNA design in CMOS 0.18µm technology. When the current is constrained to a maximum of 3mA, the LNA achieves a noise figure of 3dB and an input return loss of −40dB.