Yansi Yang, Yingyun Yang, Lipi Niu, Huabing Wang, Bo Liu
{"title":"Hardware system design of SD card reader and image processor on FPGA","authors":"Yansi Yang, Yingyun Yang, Lipi Niu, Huabing Wang, Bo Liu","doi":"10.1109/ICINFA.2011.5949060","DOIUrl":null,"url":null,"abstract":"We designed a useful digital signal generating system which transforms various file data stored in SD card into SDI output signal based on the FPGA hardware platform. This paper presents the hardware design and implementation of the system, which includes two steps. First step is the design of the NIOS II system, which includes SRAM controller and SD card controller IP core design. Second step is the generation of the whole functional SOPC system which using Quartus II development tool. NIOS II system is integrated with the scrambling encoders in this step. And then the hardware system is implemented.","PeriodicalId":299418,"journal":{"name":"2011 IEEE International Conference on Information and Automation","volume":"411 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference on Information and Automation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICINFA.2011.5949060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
We designed a useful digital signal generating system which transforms various file data stored in SD card into SDI output signal based on the FPGA hardware platform. This paper presents the hardware design and implementation of the system, which includes two steps. First step is the design of the NIOS II system, which includes SRAM controller and SD card controller IP core design. Second step is the generation of the whole functional SOPC system which using Quartus II development tool. NIOS II system is integrated with the scrambling encoders in this step. And then the hardware system is implemented.