{"title":"High performance digitally programmable CNN chip with discrete templates","authors":"F. Sargeni, V. Bonaiuto","doi":"10.1109/CNNA.1994.381705","DOIUrl":null,"url":null,"abstract":"In this paper a high performance VLSI implementation of a 3/spl times/3 Digitally Programmable Cellular Neural Network with discrete templates is presented. This chip, manufactured and successfully tested, gives an efficient solution to the hardware implementation of the Cellular Neural Networks. Moreover this chip can be connected to others to carry out very large CNN arrays. This implementation covers the 66% of the available one-neighborhood fixed templates for image processing applications.<<ETX>>","PeriodicalId":248898,"journal":{"name":"Proceedings of the Third IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Third IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNNA.1994.381705","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 24
Abstract
In this paper a high performance VLSI implementation of a 3/spl times/3 Digitally Programmable Cellular Neural Network with discrete templates is presented. This chip, manufactured and successfully tested, gives an efficient solution to the hardware implementation of the Cellular Neural Networks. Moreover this chip can be connected to others to carry out very large CNN arrays. This implementation covers the 66% of the available one-neighborhood fixed templates for image processing applications.<>