Optimization of complementary power DMOSFETs for low-voltage high-frequency DC-DC conversion

Abstract

This paper describes the trade-offs among conduction, gate drive, output capacitance, and crossover losses for complementary power DMOSFETs used in switchmode DC-to-DC converters. These are evaluated as a function of normalized die size and 11 technology related parameters. DMOSFET size optimization for a 1-MHz complementary synchronous buck converter (V/sub out/=2.7 V) and boost converter (V/sub out/=6 V) is detailed for single-cell lithium ion battery applications in the 100 mA to 1 A range of load current.<>