TCAD-SPICE simulation of MOSFET switch delay time for different CMOS technologies

Abstract

A comparison of delay time (td) for n- and p-MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to define td for the set of 3.0…0.25 um MOSFETs fabricated by the three mentioned technologies. It was shown that 0.5 um Peregrine UTSi SOS n- and p-MOSFET provided the td reduction of 220–240% in comparison with bulk silicon and 20–25% with SOI.