Performance evaluation of three Network-on-Chip (NoC) architectures (Invited)

Abstract

As the number of processing elements which can be placed on a single chip doubles about every two years, both System-on-Chip (SoC) and the microprocessor market call for high-performance, flexible, scalable, and design-friendly interconnection network architectures [1]. Network-on-Chip (NoC) has been proposed as a solution to multi-core communication problems. The advantages of NoC include high bandwidth, low latency, low power consumption and scalability. The interconnection architecture has a significant impact on the performance of networks in terms of point-to-point delay, throughput, and loss rate. We evaluate the performance of three NoC architectures, including the torus, the Metacube and the hypercube under Poisson and bit-complement traffic pattern. Network sizes of 32, 64, 128, 512 and 1024 nodes are considered. Three injection rates ranging from 10% to 30% are applied to the target networks. Performance evaluation reflects that the torus is a viable choice for small networks (32-64 nodes) and the Metacube exhibits similar performance to the hypercube for 128 nodes and 512 nodes networks under a moderate load. Lower link complexity and fewer long wires make the Metacube a cheaper alternative to the hypercube.