Guanhua Wang, Chenchang Zhan, Junyao Tang, Ning Zhang
{"title":"Dynamic-Replica-Based All-Condition-Stable LDO Regulator with 5X Improved Load Regulation","authors":"Guanhua Wang, Chenchang Zhan, Junyao Tang, Ning Zhang","doi":"10.1109/CICTA.2018.8706070","DOIUrl":null,"url":null,"abstract":"An NMOS LDO regulator using a dynamic replica to significantly improve the regulation precision is presented. By sensing the load current and dynamically adjusting the replica current, the power transistor is biased properly to improve regulation without compromising the all-condition stability of a classical fixed-replica regulator. The proposed LDO regulator is implemented in a 0.18-μm CMOS process, occupying an active chip area of 0.039 mm2. With 1.2 V input and 1.1 V nominal output voltage, the proposed design achieves 5 times improved load regulation, at the same time demonstrating stable and fast transient responses over the wide load capacitance range from 0 to virtually infinity.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICTA.2018.8706070","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
An NMOS LDO regulator using a dynamic replica to significantly improve the regulation precision is presented. By sensing the load current and dynamically adjusting the replica current, the power transistor is biased properly to improve regulation without compromising the all-condition stability of a classical fixed-replica regulator. The proposed LDO regulator is implemented in a 0.18-μm CMOS process, occupying an active chip area of 0.039 mm2. With 1.2 V input and 1.1 V nominal output voltage, the proposed design achieves 5 times improved load regulation, at the same time demonstrating stable and fast transient responses over the wide load capacitance range from 0 to virtually infinity.