Ground Plane influence on UTBB SOI nMOSFET analog parameters

Abstract

This paper presents an analysis of the Ground Plane (GP) influence on analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices based on experimental data and simulations results. The presence of a GP improves the transconductance in the saturation region due to the strong coupling between front and back gates. However, the GP worsens the output conductance due to the higher drain electrical field penetration observed by simulation. As a result, the devices without ground plane present better results in intrinsic voltage gain, Early Voltage and Drain Induced Barrier Lowering.