Design and realization of CMOS circuits using dual integrated technique to reduce power dissipation

Abstract

Many a change have been taking place in the technologies and trends in very large scale integration (VLSI) these days. The main factors in VLSI are Area, Speed and power. As there is a need of low power circuits in all real time applications like consumer electronics, medical applications, and mobile applications. So low power design theme is raised. As this paper introduces a method to reduce power dissipation in digital CMOS circuits using power gated dual sub threshold (PGDST) supply voltage. The purpose of this dual supply voltage is some of ultra-low power applications and the circuits with low supply voltages. They did not give satisfactory results with single supply voltage. This secondary supply voltage is assigned for gates, components depends on the critical path and path density in the circuit. Power gating technique is applied for corresponding circuit at supply voltage level to reduce power dissipation. This entire work is implemented in Mentor Graphics Back End Tool with Pyxis Schematic 10.3 version on Linux operating system. By using this technique high amount of power dissipation is reduced in designed circuits and increases the performance of the designed circuits.