Low Jitter and Low Power PLL：Towards The Utopia

Abstract

A PLL usually consists of a voltage controlled oscillator (VCO) locked to a reference clock Ref by a feedback loop with: a phase detector (PD), a charge pump (CP), a loop filter (LF) and a frequency divider with ratio N (÷N). Every component will add noise and power to the PLL. In an ideal case, the PLL jitter and power should be mostly determined by the VCO and Ref, while the other components like PD, CP, LF and divider adds negligible noise and consumes negligible power. This paper describes this "PLL Utopia" and discusses how it can be achieved through PLL architecture and circuit design innovations.