Native MPSoC co-simulation environment for software performance estimation

Abstract

Performance estimation of Multi-Processor System-On-Chip (MPSoC) at a high abstraction level is required in order to perform early architecture exploration and accurate design validations. Although abstract executable models provide interesting functional validation capabilities, they quickly become unsuitable when timing becomes an issue - Native software simulation, a good candidate from the speed point of view, suffers from this issue. In this paper, we present a transactional level simulation environment that allows reliable performance estimation with a specific focus on software timing estimation on multi processor architectures. The embedded software is compiled natively on the host running the simulation and instrumented to reflect its execution on a specific target processor and then executed on a simulation model of the underlying hardware. The key contribution of this work is the use of both static and dynamic analysis, that allow realistic timing measurements in native software simulation. Experimental results show the efficiency of the proposed method to accurately estimate software performance in co-simulation environments.