{"title":"Depth based 3D sharpness and contrast enhancement application on stereo images","authors":"Burak Govem, M. Sayinta, Eren Somcag, F. Donmez","doi":"10.1109/SIU.2013.6531555","DOIUrl":null,"url":null,"abstract":"In this paper, a depth based sharpness and contrast enhancement algorithm on 3D video is mentioned and implementation of this algorithm on Xilinx Spartan6 FPGAs is presented. Sharpness&contrast enhancement algorithms are ubiquitous on 2D video post-processing systems. This algorithm enhances the 3D perception by adjusting sharpness and contrast using the disparity of the objects extracted from 3D video, working with the luminance component of the image. Algorithm is implemented on a Xilinx Spartan 6 xc6slx75 chip. Resource usage and performance of the implementation are presented.","PeriodicalId":168462,"journal":{"name":"2013 21st Signal Processing and Communications Applications Conference (SIU)","volume":"68 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 21st Signal Processing and Communications Applications Conference (SIU)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIU.2013.6531555","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, a depth based sharpness and contrast enhancement algorithm on 3D video is mentioned and implementation of this algorithm on Xilinx Spartan6 FPGAs is presented. Sharpness&contrast enhancement algorithms are ubiquitous on 2D video post-processing systems. This algorithm enhances the 3D perception by adjusting sharpness and contrast using the disparity of the objects extracted from 3D video, working with the luminance component of the image. Algorithm is implemented on a Xilinx Spartan 6 xc6slx75 chip. Resource usage and performance of the implementation are presented.