Implementation of a novel LVQ neural network architecture on FPGA

Abstract

The current study presents the hard implementation methodology of a Learning Vector Quantization (LVQ) neural network on a Field Programmable Gate Array (FPGA) circuit specially suited for fast output applications. The implementation methodology is based on a mixed parallel sequential approach with the use of the L2 norm (Euclidian distance) to measure the distance between the reference vector and the prototype vector. The adopted architecture has been implemented on a device XCV1000 (FPGA Xilinx) and the given results have shown good performances in time, surface and consumption.