Implementation of LRU Replacement Policy for Reconfigurable Cache Memory Using FPGA

Abstract

Cache memory is an important part in computer systems. In set associative cache memory each incoming memory block from the main memory into cache memory should be placed in one of many specific cache lines according to the degree of associativity. In case of all ways lines are fill, a replacement policy should be designed to indicate which line of that cache memory ways will be replaced. In this paper a LRU (Least Recently Used) replacement policy has been implemented in two different methods for reconfigurable cache memory using FPGA (Field-Programmable Gate Array) and programmed using VHDL (Very high speed IC Hardware Description Language). The tree based pseudo LRU replacement policy is much simple and requires less LRU array size than Conventional LRU because it needs only 7 bits for each cache line. While the conventional LRU is easier in implemented and also require only one unit to managing the LRU replacement policy.