Mohammad J. Rashti, H. Rabiee, A. Foroutan, Meisam Lavasani
{"title":"A multi-dimensional packet classifier for NP-based firewalls","authors":"Mohammad J. Rashti, H. Rabiee, A. Foroutan, Meisam Lavasani","doi":"10.1109/SAINT.2004.1266123","DOIUrl":null,"url":null,"abstract":"In this paper we present design and implementation of a new multi-dimensional packet classifier engine using network processor technology. Our classification algorithm is fast and is based on hierarchical trie search for multi-dimensional rules. Moreover, we propose a technique to optimize the memory usage of our classifier. We have used the Intel/spl reg/ IXP1200 network processor pipeline architecture for implementation of the classifier. The final system is targeted to be a fast firewall packet filtering engine that uses the filtering policies as its classification rules. Our experimental result shows that the packet classification throughput results for various distribution of packet sizes, is above 800Mbps.","PeriodicalId":340968,"journal":{"name":"2004 International Symposium on Applications and the Internet. Proceedings.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Symposium on Applications and the Internet. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAINT.2004.1266123","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
In this paper we present design and implementation of a new multi-dimensional packet classifier engine using network processor technology. Our classification algorithm is fast and is based on hierarchical trie search for multi-dimensional rules. Moreover, we propose a technique to optimize the memory usage of our classifier. We have used the Intel/spl reg/ IXP1200 network processor pipeline architecture for implementation of the classifier. The final system is targeted to be a fast firewall packet filtering engine that uses the filtering policies as its classification rules. Our experimental result shows that the packet classification throughput results for various distribution of packet sizes, is above 800Mbps.