{"title":"Adaptive single-event effect mitigation for dependable processing systems","authors":"R. Glein, F. Rittner, A. Heuberger","doi":"10.1109/ReConFig.2016.7857149","DOIUrl":null,"url":null,"abstract":"For application in radiation-harsh environments, designers apply mitigation techniques according the worst-case (solar) condition to achieve a dependable design. This results in a resource overhead, which is most of the time unnecessary. To overcome this problem, adaptive mitigation techniques are used. This technique is a trade-off between two parameters, such as performance and reliability, according to different operating modes by toggling between these modes. In this context, we propose an Adaptive Single-Event Effect Mitigation (ASEEM) method. It is based on adaptive reconfiguration of an FPGA between two modes, specifically a performance mode and a high reliability mode. The performance mode offers high processing power and thus higher signal processing throughput. We evaluate ASEEM by calculating results with particle data from 2010 until 2016 for one space-grade and two commercial-grade FPGAs. Based on radiation data, we calculate upset rates, availability, performance and performability. We discuss one realization of ASEEM in detail with fixed upset rates. The examples presented in this paper show a reduction of the upset rate form a sixth to a ninth (compared with the performance mode) and the availability of the high processing power over 90 % in the considered time interval. We conclude that the investigated ASEEM realization is optimal for moderate and long mean times to repair. In a processing case study, with a fixed mean time to repair of one hour, we obtain a performability improvement of 14% and an availability improvement of 21 % over the performance mode for an FPGA using the latest semiconductor technology.","PeriodicalId":431909,"journal":{"name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2016.7857149","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
For application in radiation-harsh environments, designers apply mitigation techniques according the worst-case (solar) condition to achieve a dependable design. This results in a resource overhead, which is most of the time unnecessary. To overcome this problem, adaptive mitigation techniques are used. This technique is a trade-off between two parameters, such as performance and reliability, according to different operating modes by toggling between these modes. In this context, we propose an Adaptive Single-Event Effect Mitigation (ASEEM) method. It is based on adaptive reconfiguration of an FPGA between two modes, specifically a performance mode and a high reliability mode. The performance mode offers high processing power and thus higher signal processing throughput. We evaluate ASEEM by calculating results with particle data from 2010 until 2016 for one space-grade and two commercial-grade FPGAs. Based on radiation data, we calculate upset rates, availability, performance and performability. We discuss one realization of ASEEM in detail with fixed upset rates. The examples presented in this paper show a reduction of the upset rate form a sixth to a ninth (compared with the performance mode) and the availability of the high processing power over 90 % in the considered time interval. We conclude that the investigated ASEEM realization is optimal for moderate and long mean times to repair. In a processing case study, with a fixed mean time to repair of one hour, we obtain a performability improvement of 14% and an availability improvement of 21 % over the performance mode for an FPGA using the latest semiconductor technology.