A Software-Hardware Co-designed Methodology for Efficient Thread Level Speculation

Abstract

Thread-Level Speculation (TLS) mechanism has been extensively studied due to its capability of simplifying parallel programming and achieving effective performance speedup. In this paper, we investigate the study of improving current TLS models for high efficiency on present multi-core architectures. Particularly, we propose a new TLS model called Cache Copy-on-Write (CCoW). The main features of our CCoW model include: 1) software/hardware co-designed implementation of TLS; 2) more efficient sharing management of speculative variables among speculative threads to resolve loop-carried dependence; 3) a novel speculative variable storage mechanism to enhance efficiency and effectiveness of the speculative execution. A prototype for our Cache-COW is built on SESC simulator and experimental results indicate that the proposed CCoW accelerates typical benchmarks by an average of 5.69x and 10.04x using 8 and 16 speculative threads respectively.