Design of the 65-nm CMOS translation lookaside buffer on the hardened elements

Abstract

The translation lookaside buffer is designed on the base of STG DICE cells with transistors which are spaced into two groups together with transistors of the output combinational logic. The elements contain two spaced identical blocks for the resistance to impacts of single nuclear particles compared to elements on 6-transistors memory cells. Basic elements that were used have no upsets of states during simulations at the linear energy transfer on tracks up to 60 MeV×cm2/mg. In combinational logic of the elements of matching and masking short-term noise pulses can occur.