E. Miersch, M. Gospodinova, G. Nan, J. Thomas, J. Held
{"title":"Electrical high speed chip-package characterization comparison of simulation results with component measurement","authors":"E. Miersch, M. Gospodinova, G. Nan, J. Thomas, J. Held","doi":"10.1109/SPI.2004.1409056","DOIUrl":null,"url":null,"abstract":"The electrical characteristics of interconnects (signal and power nets) of a given multi-chip package (MCP) had to be determined. MCP-nets are mostly multi drop (multi point) nets (MDNs) with in this case up to 18 terminals. The given clock frequency range is 200MHz to 500MHz. The outer dimensions of the MCP under test (MCP u.t.) are about 11 /spl times/ 12mm. The goal of the analysis was to find out an appropriate way of modelling for such a complex package including signal as well as power nets. It was also necessary to understand if the MCP multi-port nets can be described as lumped circuits in the given performance range of 200MHz to 500MHz as predicted by the /spl lambda//20 - and the t/sub s/ > 5t/sub f/ - rules for the about 1cm long partial branches of the MDNs.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPI.2004.1409056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The electrical characteristics of interconnects (signal and power nets) of a given multi-chip package (MCP) had to be determined. MCP-nets are mostly multi drop (multi point) nets (MDNs) with in this case up to 18 terminals. The given clock frequency range is 200MHz to 500MHz. The outer dimensions of the MCP under test (MCP u.t.) are about 11 /spl times/ 12mm. The goal of the analysis was to find out an appropriate way of modelling for such a complex package including signal as well as power nets. It was also necessary to understand if the MCP multi-port nets can be described as lumped circuits in the given performance range of 200MHz to 500MHz as predicted by the /spl lambda//20 - and the t/sub s/ > 5t/sub f/ - rules for the about 1cm long partial branches of the MDNs.