Monte Carlo investigation of optimal device architectures for SiGe FETs

Abstract

Strained silicon channel FETs grown on virtual SiGe substrates show clear potential for RF applications, in a material system compatible with silicon VLSI. However, the optimisation of practical RF devices requires some care. 0.1-0.12 /spl mu/m gate length designs are investigated using Monte Carlo techniques. Although structures based on III-V experience show f/sub T/ values of up to 94 GHz, more realistic designs are shown to be limited by parallel conduction and ill constrained effective channel lengths. Aggressively scaled SiGe devices, following state-of-the-art CMOS technologies, show f/sub T/ values of up to 80 GHz.