Quarter-Rate Implementation of an 1 GSPS 128 Tap FIR Structure used as Cross-correlator in UWB Communication

Abstract

Finite impulse response (FIR) filters are widely used in many applications involving signal processing algorithms. The FIR can also be used as a convolver or as a cross-correlator due to its structural similarity. In general the problem with the hardware implementation of FIR is mainly the area complexity and this is much prominent if the number of taps is pretty large. For high throughput application, like UWB communication, the designer is forced to go for parallel-pipelined design and this increases the complexity many fold. Parallel architecture is required not only to meet the stringent throughput requirement but also to save power consumption. However an L level parallelization typically increases the number of computations (multiplications + additions) by L times compared to a single level FIR architecture. This increases the area complexity around L times. Typically the area complexity of multiplier is much more than an adder. A significant amount of research work has been conducted to reduce the multiplication complexity of FIR architecture. In this paper we present an adder-tree based multiplier block parallel FIR architecture which reduces the multiplication complexity in many fold compared to standard multiplier based or Canonic Signed Digit (CSD) based multiplier architecture. We also present a simple way of forming the exhaustive adder-tree multiplier block.