An efficient FPGA-based direct linear solver

Abstract

This paper presents a novel method to finding the solution to a system of linear equations efficiently by using a reconfigurable hardware based real-time computational solver. The presented linear solver is to directly solve the system of linear equations through repetitively applying Gauss-Jordan elimination to each column of an augmented matrix in parallel on reconfigurable hardware, which can greatly accelerate the solution procedure. Backward substitution is not needed, so the computing latency can be further reduced. The main components of the hardware solver include parallel data processing modules, reusable memory blocks and flexible control logic units. By considering pivoting, this solver can avoid the potential problem of increasingly-large numbers after row operations. The salient feature is that the latency of this solver is really low through parallel processing, deep pipelining and flexible use of memory blocks. For instance, the total latency of this linear solver is controlled below 1000 clock cycles for a dense system of dimension 32. On a Xilinx Vertex 6 FPGA of 200MHz, which has a clock cycle of 5ns, the minimum latency can be as low as 5 microseconds. Applications of this hardware accelerated linear solver may include, but are not limited to, real-time least square estimation for sensor data, digital signal / video processing and real-time circuit simulation. It can also find wide applications in mathematical computing such as finding the inverse of a matrix, computing determinants or ranks of matrices, etc.