Accelerated logic simulation using parallel processing

Abstract

The author presents a modified time-warp algorithm for parallel logic simulation using circuit partitioning. The algorithm allows a processor to roll back its simulation time to any given point in the past, only using the input queue. The memory space for the state queue and the output queue and the computing effort to handle them can be saved. A software model of a distributed system has been developed as test environment for the implementation of the modified algorithm, which is compared with the link time algorithm and with a sequential simulation. It is shown that the speedup of the time-warp method is less dependent on cycles in the communication graph (feedbacks in the test-circuit) than the link time method.<>