Analysis of a Transistor Count Optimized Charge Pump for Telecommunication Application

Abstract

The progress in the design of a charge pump (CP) circuit has noted some vital non-idealities such as current mismatch, phase noise and reference spur. Also, lock-in time is considered as one of the most important attributes for which a high-performance CP design always remains as an open challenge for potential application in high-speed mobile communication. This article explores an Operational Amplifier (Op-amp) based optimal gate count CP designed for 90nm CMOS using CADENCE Virtuoso platform at a supply voltage of 1.2Volt to burn as small as 226uW of power. The measured phase noise and reference spur are -117.3 dBc/Hz and -113.8 dBc/Hz at an offset frequency of 10MHz. The reported locking time of 9.15ns only with a current mismatch of 0.22% makes it competent enough for PLL driven communication modules.