A new 12-b 40 ms/s, low-power, low-area pipeline ADC for video analog front ends

Abstract

A 12-bit, 40 MS/s pipelined analog-to-digital converter (ADC) is designed in 0.18-/spl mu/m CMOS technology with 1.8 V single power supply. The proposed ADC architecture uses a combination of current-mode and voltage-mode stages to, significantly, reduce both power dissipation and area compared to conventional fully differential voltage-mode pipeline ADCs. Simulation results are provided and indicate that the proposed ADC has potential to be deployed in the video analog front-ends.