Ting-Hsu Chien, Chi-Sheng Lin, D. Chang, Y. Juang, Chun-Ming Huang
{"title":"A high sensitivity, low power Phase Controlled Current Source for Gsamples/s phase-locked loops","authors":"Ting-Hsu Chien, Chi-Sheng Lin, D. Chang, Y. Juang, Chun-Ming Huang","doi":"10.1109/MWSYM.2008.4633149","DOIUrl":null,"url":null,"abstract":"Operating up to 3.2-GHz with power consumption of 1.32mW, a Phase Controlled Current Source (PCCS) capable of both phase frequency comparing and current providing is presented. Benefiting from simple, feed-forward operation characteristic, the PCCS minimizes the short current issue while maintaining free dead zone feature. The phase and frequency sensitivities of the PCCS have been measured to demonstrate its performance. With a reference source ranging from 2.1-GHz to 3.2-GHz, a PLL embedding the PCCS achieves phase noise around −100 dBc/Hz at 1-kHz offset. The lowest phase noise at 1MHz offset is −131 dBc/Hz when the PLL uses a 2.3-GHz reference source.","PeriodicalId":226779,"journal":{"name":"Intelligent Memory Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Intelligent Memory Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2008.4633149","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Operating up to 3.2-GHz with power consumption of 1.32mW, a Phase Controlled Current Source (PCCS) capable of both phase frequency comparing and current providing is presented. Benefiting from simple, feed-forward operation characteristic, the PCCS minimizes the short current issue while maintaining free dead zone feature. The phase and frequency sensitivities of the PCCS have been measured to demonstrate its performance. With a reference source ranging from 2.1-GHz to 3.2-GHz, a PLL embedding the PCCS achieves phase noise around −100 dBc/Hz at 1-kHz offset. The lowest phase noise at 1MHz offset is −131 dBc/Hz when the PLL uses a 2.3-GHz reference source.