Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer

Abstract

In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.