Optimization of GGNMOS Devices for High-Voltage ESD Protection in BCDLite Technology

Abstract

Design optimization of Electrostatic Discharge (ESD) GGNMOS for high-voltage applications in low-cost BCDLite technology is reported. Clamp performance optimization through body PWELL engineering and device design techniques are investigated. A comparative analysis between two distinct device architectures (different Poly-LOCOS overlap) showing 100ns TLP measurement and TCAD simulation results is presented.