Effects of intrinsic layer thickness variations on heterojunction Pin Diode I–V characteristics

Abstract

A heterojunction PIN Diode in which an intrinsic layer (I-layer) of In0.53Ga0.47As is sandwiched between N-layer of In0.52Al0.48As and p-layer of In0.53Ga0.47As is modelled and investigated using TCAD simulation. At all ternary uniformly doped epitaxial growth is assumed for all layers with abrupt heterojunction interfaces. Since the epitaxial design of I-layer is most critical in PIN diode operations, the thickness of I-layer is varied in TCAD simulation to calculate maximum leakage current and breakdown voltage in reverse bias operation, and turn on voltage at forward bias operation. By optimizing epitaxial structure of I-layer, we have demonstrated improved DC characteristics for modelled device. S-parameters are then calculated and discussed for a Single Pole Single Throw (SPST) switch configuration of PIN Diode.