Thermal-Aware Optimization of SoC Floorplan with Heterogenous Multi-Cores

J. Yoo, Taekeun An, Chi-young Oh, Youngsang Cho, Heeseok Lee, Yunhyeok Im, Minkyu Kim, Minsu Kim
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引用次数: 3

Abstract

As the performance required by System on Chip (SoC) IPs has increased, power consumption and power density have been increased. Since the SoC temperature is increasing, thermal-aware design in SoC, package, and system must meet the required target performance and reliability. Thermal-aware floorplan is an important aspect because self-heating and thermal coupling differ depending on the absolute and relative location of each IP. Moreover, it can be considered highly effective as it costs less than package and system solutions. In this paper, we demonstrate a thermal-aware floorplan optimization method considering the physical design elements of multi-core design in SoC. It also describes a method to reduce the SoC temperature comprehensively. In multi-cores, heating modules (HotSpot Area) must be separated from each other due to mutual thermal coupling. It is comfirmed by thermal simulation that the thermal resistance is much lower than that of all the attached heating modules. Also, Temperature can be reduced at the early design stage by placing the IPs appropriately in the available region across the SoC based on Cooling Zone (CZ), Keep Out Zone (KOZ), and Acceptable Zone (AZ). Simulation results indicates that the effect of thermal-aware floorplan is dominant when compared to package and system.
异构多核SoC平面设计的热感知优化
随着片上系统(SoC) ip对性能要求的提高,功耗和功率密度也在增加。随着SoC温度的不断升高,SoC、封装和系统中的热感知设计必须满足所需的目标性能和可靠性。热感知平面图是一个重要的方面,因为自热和热耦合取决于每个IP的绝对和相对位置。此外,它可以被认为是非常有效的,因为它比封装和系统解决方案的成本更低。在本文中,我们展示了一种考虑SoC中多核设计的物理设计元素的热感知布局优化方法。介绍了一种全面降低SoC温度的方法。在多核环境下,发热模块(HotSpot Area)之间存在热耦合,需要相互隔离。通过热模拟证实,其热阻远低于所附发热模块的热阻。此外,通过将ip适当地放置在基于冷却区(CZ),保持区(KOZ)和可接受区(AZ)的SoC可用区域中,可以在早期设计阶段降低温度。仿真结果表明,与封装和系统相比,热敏感平面图的影响占主导地位。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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