{"title":"Data Block Partitioning for Recovering Stuck-at Faults in PCMs","authors":"Marjan Asadinia, Majid Jalili, H. Sarbazi-Azad","doi":"10.1109/NAS.2017.8026850","DOIUrl":null,"url":null,"abstract":"Main burdens to the DRAM scalability are leakage and charge storage restrictions. Phase Change Memory (PCM) is being known as a promising candidate for the replacement of DRAM among competitive non-volatile memories. However, this memory suffers from low cell reliability due to limited write endurance. This problem can lead to some memory cells permanently stuck at either '0' or '1'. Therefore, a robust error recovery scheme is needed to overcome this problem and recover from hard errors. State-of-the-art solutions apply error correction and recovery techniques at inter- line or intra-line level. Precisely, they can improve PCM endurance either by remapping failed lines to spares (in inter-line level schemes) or by using data-block partitioning and bit- inversion scheme (in intra-line level schemes). Although techniques of the latter type are effective, proper partitioning of data blocks and spreading out faults across different groups are required. In this paper, we propose and evaluate a novel intra-line level scheme that statically partition a data-block into some groups and efficiently recover multi-bit stuck-at faults per partition. This method benefits from the advantage of a simple shifting mechanism in order to increase the chance of storing data in presence of failed cells. Evaluation results for multi- threaded workloads show enhancement in the number of recoverable failures and improvement of lifetime over existing techniques.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Networking, Architecture, and Storage (NAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAS.2017.8026850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Main burdens to the DRAM scalability are leakage and charge storage restrictions. Phase Change Memory (PCM) is being known as a promising candidate for the replacement of DRAM among competitive non-volatile memories. However, this memory suffers from low cell reliability due to limited write endurance. This problem can lead to some memory cells permanently stuck at either '0' or '1'. Therefore, a robust error recovery scheme is needed to overcome this problem and recover from hard errors. State-of-the-art solutions apply error correction and recovery techniques at inter- line or intra-line level. Precisely, they can improve PCM endurance either by remapping failed lines to spares (in inter-line level schemes) or by using data-block partitioning and bit- inversion scheme (in intra-line level schemes). Although techniques of the latter type are effective, proper partitioning of data blocks and spreading out faults across different groups are required. In this paper, we propose and evaluate a novel intra-line level scheme that statically partition a data-block into some groups and efficiently recover multi-bit stuck-at faults per partition. This method benefits from the advantage of a simple shifting mechanism in order to increase the chance of storing data in presence of failed cells. Evaluation results for multi- threaded workloads show enhancement in the number of recoverable failures and improvement of lifetime over existing techniques.