Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 um CMOS technology

Abstract

In this study, three major reliability aspects, hot carrier effects, latchup and Electrostatic Discharge (ESD) have been simultaneously studied on a 0.25 μm CMOS technology. For this purpose, three source-drain architectures processed on different kinds of substrate were compared with respect to these three reliability aspects. This work clearly demonstrates the dependence existing between them. The source-drain architecture affects of course the hot carrier reliability but also the ESD performances. A thinner epitaxial substrate is effective to reduce latch-up occurrence, but degrades the ESD failure threshold.