Sub-sircuit model of fully-depleted double-gate FinFET including the effects of oxide and interface trapped charge

Abstract

In this paper, a method for including the effects of oxide and interface trapped charge in standard SPICE model of fully-depleted double-gate FinFET is described. It is based on the auxiliary sub-circuit connected in series with the gate input of FinFET which accounts for the bias-dependent voltage shifts due to the trapped charge. The sub-circuit model efficiency is verified using two-dimensional TCAD device simulations.