Methodology for ULSI LOCOS isolation built-in reliability analysis

Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 1997-07-21 DOI:10.1109/IPFA.1997.638065

K.V. Loiko, I.V. Peidous, H. Ho, E.K.B. Quek, D.H.Y. Lim

引用次数: 0

Abstract

The results of studying the mechanisms of CMOS ULSI LOCOS isolation failures and an effective approach to qualifying the technological processes of isolation manufacturing are presented. The described method for reliability analysis allows one to reveal the potential capability of a current technology.

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ULSI LOCOS隔离内置可靠性分析方法

本文对CMOS ULSI LOCOS隔离失效机理进行了研究，并提出了一种有效的隔离制造工艺流程的确定方法。所描述的可靠性分析方法允许人们揭示当前技术的潜在能力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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