Low Power Device Phase Locked Loop with Gm-Boosted Charge Pump and ESD Protection

Abstract

This article presents a low consumption phase locked loop (PLL) with electrostatic discharge (ESD) and use gain-boosted charge pump organization and a divided by 48 pulse swallow dividers. By gain-boosted technique can efficient to reduce the PLL reference spurs. The PLL consume of power is 6mW from 1.8V souring. The phase noise of the PLL is - 86.71 dBc/Hz at 1MHz offset and spurs are -32.64 dB. The PLL fully integrated and processing in UMC 0.18μm and it occupies 698μm×848μm active chipset area.