S.N. Pratapneni, C. Wolff, P. Hsu, J. Rozenblit, J. Prince
{"title":"Development of chip model library for the computer-aided analysis of electronic packages","authors":"S.N. Pratapneni, C. Wolff, P. Hsu, J. Rozenblit, J. Prince","doi":"10.1109/IEMT.1993.398172","DOIUrl":null,"url":null,"abstract":"The development of a chip model library for the complete design and simulation of multichip assemblies is discussed. The simulation of the driver/receiver part of the chips mounted in multichip modules (MCMs) can be done using a variety of models at varying levels of complexity. A hierarchy is used to organize the models for use with an intelligent model selection tool. Model selection is based on the tradeoff between accuracy and speed. The four models considered are device, table-based equation-based and simple RC models. The basic RC model, a physical model, considers transistor on-resistance and load capacitance as a complete representation of the driver circuit. The table lookup approach stores a detailed transfer function of device operation or circuit operation in a table using a device level circuit simulator. Equation-based models simplify the physical device equations based on the switching behavior of a particular circuit. An integral environment with this group of models is developed with an object-oriented approach. Each of the model templates is treated as an object and it can be repeated as required.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1993.398172","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The development of a chip model library for the complete design and simulation of multichip assemblies is discussed. The simulation of the driver/receiver part of the chips mounted in multichip modules (MCMs) can be done using a variety of models at varying levels of complexity. A hierarchy is used to organize the models for use with an intelligent model selection tool. Model selection is based on the tradeoff between accuracy and speed. The four models considered are device, table-based equation-based and simple RC models. The basic RC model, a physical model, considers transistor on-resistance and load capacitance as a complete representation of the driver circuit. The table lookup approach stores a detailed transfer function of device operation or circuit operation in a table using a device level circuit simulator. Equation-based models simplify the physical device equations based on the switching behavior of a particular circuit. An integral environment with this group of models is developed with an object-oriented approach. Each of the model templates is treated as an object and it can be repeated as required.<>