Assembly program verification for multiprocessors with relaxed memory model using SMT solver

Abstract

A relaxed memory model allows reordering of memory accesses, which can violate program correctness in multiprocessors. This paper presents an approach to verifying a list of assembly programs under a relaxed memory model. Assembly programs are considered for abstractions, which capture essential information that affects the correctness. For program verification, SMT solvers are adopted for finding an execution that violates program property, which is defined by assertions. The solver takes constraints that represent the violation of assertion conditions to find a valuation which can construct an execution. An encoding method is presented for constructing the constraints of program behavior, which classifies the essential behaviors in multiprocessors and can be used by the solvers. An automated tool was developed to abstract the list of assembly programs and find an execution that violates the program assertions. Experiment results show the tool can verify assembly programs for SPARC architecture under SC, TSO, and PSO memory models.