Static Noise Margin of 6T SRAM Cell in 90-nm CMOS

Abstract

This paper examines the factors that affect the Static Noise Margin (SNM) of a 6T Static Random Access Memory (SRAM) cell designed in 90-nm CMOS. In this paper, the SRAM cell is simulated and noise margins are obtained while varying several parameters that affect SRAM operations. These parameters are temperature, threshold voltage, supply voltage, cell ratio, pull-up ratio, and process corner variations. The simulation results were found to be in agreement with the model derived by Seevinck et al. [1] which is based on the square law device model.