SID-Mesh: Diagonal Mesh Topology for Silicon Interposer in 2.5D NoC with Introducing a New Routing Algorithm

Abstract

Silicon interposer technology or 2.5D stacking is an approach to decrease memory access delay. In the 3D stacking method, the memory stacks are placed on top of the processing chip, and it uses Through Silicon Via vertical links, but in the 2.5D method, the stacked memories are placed on the sides of the processing chip, and data transfer is from the network that lays on the silicon interposer. We examine the interposer network topologies in the 2.5D chip and present Diagonal Mesh with a new routing algorithm for the interposer network. The stacked memories are on two sides of the processing chip, so Diagonal Mesh interconnections can reduce the delay in accessing dynamic memory using diagonal links. Symmetry and short diagonal links are the advantages of the Diagonal Mesh compared to the other topologies. According to the simulation results, the Diagonal Mesh average hop count is lower than Concentrated Mesh and Double Butterfly, and the average packet latency is lower than the compared topologies. Diagonal Mesh improved 19.7 percent in the average hop count and 41.17 percent in the network saturation point compared to Concentrated Mesh.