{"title":"Mixed signal neural circuits for shortest path computation","authors":"N. Shaikh-Husin, J. Meador","doi":"10.1109/ACSSC.1995.540825","DOIUrl":null,"url":null,"abstract":"The objective of the graphical shortest path problem is to discover the least cost path in a weighted graph between a given source vertex and one or more destinations. This problem class has numerous practical applications including data network routing and speech recognition. This paper discusses the hardware realization of a recurrent spatiotemporal neural network for single source multiple-destination graphical shortest path problems. The network exhibits a regular interconnect structure and uses simple processing units in a combination which is well suited for VLSI implementation with a standard fabrication process.","PeriodicalId":171264,"journal":{"name":"Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1995.540825","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The objective of the graphical shortest path problem is to discover the least cost path in a weighted graph between a given source vertex and one or more destinations. This problem class has numerous practical applications including data network routing and speech recognition. This paper discusses the hardware realization of a recurrent spatiotemporal neural network for single source multiple-destination graphical shortest path problems. The network exhibits a regular interconnect structure and uses simple processing units in a combination which is well suited for VLSI implementation with a standard fabrication process.