Performance evaluation of a composite on-chip cache in a single bus processor

Abstract

Presents simulation results of a composite on-chip cache, for a single bus RISC processor, that can provide an alternative to a stall cache or an instruction cache. The composite cache consisting of a small stall and data cache provides better performance than individual caches of comparable hardware complexity. Furthermore, our evaluation of different replacement policies reveals that a random replacement policy yields a performance that matches and in many cases exceeds the performance (up to 5%) of more complex replacement policies.