Digital building block for frequency synthesizer and fractional phase locked loops

Abstract

The paper describes a new architecture of a digital building block, which can be used in frequency synthesizers and phase locked loops. The circuit is based on generators, counters and a register. The technique described here is much simpler then other methods. The presented synthesizer is the most suitable for the design of VLSI architectures or for programmable large scale integration (or in-system programmable large scale integration). One of the main advantages is stability and pure digital structure. On the other hand, this synthesizer has a disadvantage in its low output frequency, but this can be overcome by using it together with a phase locked loop.