Reconfigurable hardware implementation of gigabit UDP/IP stack based on spartan-6 FPGA

Abstract

This paper presents a very high speed FPGA implementation of UDP/IP stack. It not only can be a solution to FPGA-external world communication, but also can be regarded as a network node. The physical layer and its interface to the FPGA's IO Blocks are pre-implemented off-the-shelf using an integrated gigabit Ethernet transceiver (Marvell 88E1111) which supports BASE-T standard. The link layer is based on Xilinx Tri-Mode Ethernet MAC core. A novel architecture of transport and network layers by means of both fabric and dedicated FPGA blocks is also proposed which can provide a PC-FPGA and vice versa gigabit data communication. A software program which sends and receives data in connected PC is also developed in MATLAB using DSP System Toolbox. Compared to previous works, the proposed system shows a noticeable speed-up, suitable for FPGA based data streaming applications. Both post place and route simulation and practical tests corroborate validity of the proposed system.