Low power design of Johnson Counter using clock gating

Abstract

Power dissipation minimization is one of the prime concerns in recent VLSI design. As chip size is shrinking and many other micro-electronics reliabilities are developing gradually, low power design of any system has become priority. Computer system consists of sequential circuits mostly and that is why efficient low power design of various sequential circuits is very important. In this paper, we have proposed a low power design scheme of Johnson Counter using clock gating system. Doing some power analysis in SPICE, it is considered that our proposed system has lower power dissipation and simpler interconnections compared to the conventional design.