2.5 GHz Data Rate 2 × VDD Digital Output Buffer Design Realized by 16-nm FinFET CMOS

Abstract

A 2 × VDD output buffer equipped with SR (slew rate) self-adjustment mechanism driven by a PVT (process, voltage, temperature) detector is proposed in this investigation. Notably, the proposed buffer design is realized by 16-nm FinFET CMOS technology, where specical design constraints required by FinFET must be taken into consideration. In other words, design trade-off will be discussed and highlight. To enhance the output SR, awlays-on driving transistors in Output Stage must be realized with low Vth devices to boost the output current. For FinFET devices, The gate drives of these driving transistors must be stablized to prevent any possible noise interference. Nonoverlapping signaling control is directly realized in transistor level instead of conventional gate level designs such that the the speed is fastened. According to the all-PVT-corner simulations, the worst data rate is 2.5/2.5 GHz with 20 pF loading when the supply voltage is 0.8/1.6 V, respectively. The ∆ SR improvement is at least 10%, when the proposed SR self-adjustment mechanism is activated.